Intentionally grown interfacial layer (IL) is used in order to arrange a good interface between the silicon surface (i.e. the surface of a substrate) and the gate insulator, especially with high-k dielectrics (e.g. HfO2, HfSiO4, ZrO2, ZrSiO4, etc.), and to suppress the mobility degradation of the channel carrier of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs).
Previously, chemical oxide prepared by diluted HF, Standard Clean 1 (SC1), and Standard Clean 2 (SC2), and thin oxide layers by In-Situ Silicon Growth (ISSG), Enhanced In-Situ Silicon Growth (EISSG), Rapid Thermal Oxidation (RTO), etc., were used as IL's in gate stacks, which reaches the limit around 0.8˜1.0 nm.
For example, chemical oxide is grown on silicon surface during wet cleaning and rinsing operations, highly hydrated with composition departing from stoichiometric SiO2 (SiOx with x<2). SC1 is a cleaning solution, Ammonia hydroxide-hydrogen Peroxide-water Mixture (APM, typically 0.25:1:5), used primarily to remove particles from the surface, and also capable of removing surface organics. SC1 forms chemical oxide on Si surface, and is applied at temperature between 40 and 70° C., typically combined with megasonic agitation. SC2 is another cleaning solution, hydrochloric acid-hydrogen peroxide-water mixture (HPM, typically 1:1:5), used primarily to remove metallic contaminants. Also, RTO grows an oxide layer on Si surface during high temperature and short time (typically <60 sec) exposure to oxygen containing ambient.
High-k and metal gate (HK/MG) stacks were used for generations beyond 45 nm technology due to their excellent leakage performance from high-k materials having thicker physical thickness but the same equivalent oxide thickness (EOT). In general, capacitive effective thickness (CET) of 45 nm transistors after thermal budget process is around 1.4 nm, which includes quantum mechanical thickness, EOT of HK, and IL layers. IL thickness is accordingly around 0.8˜1.0 nm.
Following the scaling trend, the CET of 32 nm technology and beyond would require EOT of IL layer at least around 0.7 nm (0.6˜0.8 nm). The previous methods for IL preparation would not be sufficient to meet this requirement. Besides, the OH termination bonding would be necessary for high-k film deposition, especially for inorganic precursors. This would preclude the potential processes such as HF last pre-clean process, due to its lack of OH bonding for high-k film deposition for inorganic precursors.
Accordingly, new methods are desired to reduce the EOT of IL, thus scale down the CET of a gate stack.